The design and optimization of an integrated circuit follows a design flow that utilizes a multi-level hierarchy of circuit specifications. At the highest level is the functional or architectural specification of the circuit. At the lowest level are placed transistors that can be used to generate masks for fabrication. Today, design flows are often based on standard cells, in which a library of low level circuits are generated, manually or automatically, and the design process selects cells from the library that match the circuit specifications.
In a typical design flow, referred to as a synthesis and place-and-route (or SPR) flow, a fixed set of cells—called a library—is used to map a given design into a physical implementation. The number of cells, and the amount of optimization that can be performed, is limited. This approach is less efficient than arbitrary full-custom design. Limitations on fixed or static libraries have been necessary because SPR tools do not efficiently automate design at the transistor level. As a result, cell generation has not been included in the EDA design flow and has been largely done by hand. Furthermore, with the advent of third-party library companies, library creation is often out-sourced.
One reason that SPR flows result in sub-optimal designs is due to limitations on the size of the cell libraries, and on the optimization process itself. Typically, logically equivalent cells in a library are provided according to a binary scale of drive strength. For example, 1×, 2×, 4×, 8× and 16× drive strength NAND gate cells are provided in a cell library. The optimization process can then only select one of these five drive strengths of logically equivalent cells to optimize a circuit.
The process of creating a large number of cells scaled to different drive strengths can be automated. However, this merely creates an oversize cell library that cannot be utilized effectively by current design tools. Most current design tools assume there will be only approximately five electrical variations for each logical function, and assume binary scaling of cells. Furthermore, a large amount of time would be needed to synthesize each scaled cell, and the size of the libraries themselves would get cumbersome. Finally, simply optimizing a design across a large number of possible cells may result in an unnecessarily large number of minor variations, many of which do not affect the overall performance.